The invention concerns a method for generating electrical conducting or semiconducting structures in two or three dimensions in a composite matrix, wherein the matrix comprises none or more materials provided in spatially separate and homogenous material structures, wherein the materials in response to the supply of energy can undergo specific and/or chemical changes of state which cause transition from an electrical non-conducting state to an electrical conducting or semiconducting state or vice versa, or a change in the electrical conduction mode of the material, and wherein each material structure is made in the form of a thin layer. The invention also concerns a method for erasing globally electrical conducting or semiconducting structures generated in two or three dimensions in a composite matrix, wherein the matrix comprises two or more material provided in spatially separate and homogenous material structures, wherein the materials in response to the supply of energy can undergo specific and/or chemical changes of state which cause transition from an electrical non-conducting state to an electrical conducting or semiconducting state or vice versa, or a change in the electrical conduction mode of the material, and wherein each material structure is made in the form of a thin layer. Finally, the invention concerns an electric field generator/modulator (EFGM) for patterning and generating electrical conducting or semiconducting structures in two or three dimensions in a composite matrix, wherein the matrix comprises one or more materials respectively provided in one or more spatially separate and homogenous material structures, wherein the materials in response to the supplied energy can undergo specific and/or chemical changes of state which cause transition from an electrical non-conducting state to an electrical conducting or semiconducting state and vice versa, or a change in the conduction mode of the material, and wherein each material structure is made in the form of a thin layer.
More particularly the present invention concerns the fabrication of two- and three-dimensional isolating, resistive, conducting or semiconducting patterns and structures for use in electronic circuits which most particularly consist of a single or several stacked layers of thin films.
The evolution of microelectronic technology shows a steady trend towards smaller dimensions and reduced costs of the devices. Well-substantiated predictions show that the performance is going to increase, while the price per unit or device will decrease. However, today""s microelectronic technology is substantially based on crystalline silicon and shows an increasing tendency towards diminishing returns, mainly due to the inherent limitations associated with the complexity of ultra-high resolution lithography and increasing demands of the material processing. Extrapolations of the present technologies based on crystalline silicon may hence not be expected to offer dramatic breakthroughs in regard of either performance or price and future improvements shall require manufacturing plants and manufacturing equipment which are extremely capital-intensive.
Microelectronics based on thin-film technology may on the other hand confidently be predicted to deliver in the near future products representing real breakthroughs in regard of performance as well as of price. The shift from crystalline inorganic semiconductors to microcrystalline, polycrystalline or amorphous inorganic or organic semiconductors will introduce entirely novel boundary conditions with regard to the production of microelectronics and particularly by the blanks having form factors which make large areas possible, i.e. the substrates may be large sheets instead of wafers cut from blanks of limited size, and great flexibility with regard to architectures, something which will be essential factors in the expected development of tomorrow""s electronic technology. In the present invention special emphasis will be placed on the use of organic materials due to the ease whereby they may be processed with basis in the use of large areas and multilayer blanks will precisely controllable thickness, as well as their vast potential for chemical tailoring of the desired material properties.
Particularly before the use of electronics based on amorphous materials can fulfill their expected potential, further developments in certain areas are required. In the recent years an effort has been made to improve the semiconducting properties of organic semiconducting thin-film materials, which have given dramatic and rapid increase in the transistor performance up to a point where organic-based transistors may now compete with transistors based on amorphous silicon (see for instance Y. -Y. Lin, D. J. Gundlach, S. F. Nelson ad T. N. Jackson, xe2x80x9cPentacene-Based Organic Thin Film Transistorsxe2x80x9d, IEEE Transactions on Electron Devices, August 1997). Other on-going projects will lead to coating processes for thin film in order to generate organic and amorphous silicon semiconductors at low temperatures and with compatibility to a broad range of organic and inorganic substrate materials. This has lead to the development of extremely cheap electronic devices with large areas based on the use of high-volume manufacturing methods.
In spite of this development a wholly satisfactory solution to how the fabrication technology shall be adapted and made suitable for a low-cost flexible high-volume production of electrical connections in the thin-film structures forming the electronic circuits is still lacking. Currently thin-film devices are based on amorphous silicon manufactured with current paths and conductors patterned with traditional methods such as lithography and vacuum metallization. The latter method has formerly also been applied to circuits for demonstration of organic-based semiconductor thin-film devices (see for instance A. R. Brown and al. xe2x80x9cLogic gates made from polymer transistors and their use of ring oscillatorsxe2x80x9d, Science 270:972-974 (1995)). Alternatively, screen printing with conducting xe2x80x9cinkxe2x80x9d has been used to make transistors on flexible polymer substrates (see for instance F. Garnier and al., xe2x80x9cAll-polymer field-effect transistor realized by printing techniquesxe2x80x9d, Science 265:1884-1886 (1994)). Even though lithography may provide high resolution, it is relatively complex and includes typically wet chemistry steps which are undesirable in high-volume production of multilayer organic thin-film structures. Screen printing with ink is also far from ideal, as it only provides low to moderate resolution besides being a xe2x80x9cwetxe2x80x9d method.
As examples of prior art such it is evident from available patent literature may also be mentioned U.S. Pat. No. 5,043,251 (Sonnenschein and al.) which discloses a process for three-dimensional lithography of amorphous polymers for generating a momentary permanent pattern in a polymer material and which comprises steps for providing doped non-crystalline layers or films of a polymer in a stable amorphous state under humane operating conditions. In manufacturing the patterns the film is masked optically and is exposed through the mask to radiation with sufficient intensity to cause ablation of the exposed portions such that a distinct three-dimensional imprint is generated in the film. This process has among other been proposed for use in the manufacture of an optical data storage disk. Further it is from U.S. Pat. No. 5,378,916 (Mantell) known a photo-sensitive device in the form of a single-crystal structure, wherein different portions of the structure may have different compositions. Particular the structure forms a two-dimensional array and a first photosensitive portion comprises a material which generates electron-hole pairs when it is exposed to light within a predetermined first wavelength range, while another photosensitive portion comprises a material which is adapted to generate electron-hole pairs when it is exposed to light within another wavelength range distinctively different from the first wavelength range. Yet further it is from U.S. Pat. No. 5,677,041 (Samyling) known a transistor device which is made by forming a doped layer of radiation-sensitive material on a substrate. The radiation-sensitive material may among others be polyimid, polymer, an organic dielectric, a conductor or a semiconductor. The substrate may be silicon, quarts, gallium arsenide, glass, ceramic, metal or polyamid. A neutral or undoped layer of another radiation sensitive material is formed over the doped layer. First and second source/drain areas are then formed in the neutral layer and extend down to a top portion of the doped layer. A gate area is formed in the top portion of the neutral layer between the first source/drain area and the second source/drain area such that a channel area in the doped layer is provided under the gate area. Drain/source and gate electrodes as formed by irradiation of the uppermost neutral layer through a mask patterned in accordance with the desired electrode pattern and realized such that it intensity-modulates the radiation. In addition the mask may also be realized as a phase-shifting mask.
Finally it is from the article xe2x80x9cPolymeric integrated circuits and light-emitting diodesxe2x80x9d of D. M. de Leeuw and al., IEDM, pp. 331-336 (1997) known a MISFET wholly realized in polymer and with the use of polymer materials which are given the desired electrical properties by an exposure to UV radiation. In the manufacture photochemical patterning of doped electrical conducting polyaniline films, so-called PANI thin films is used. The films are dissolved in a suitable solution, whereafter a photo-initiator is added to the solution which has been deposited on a suitable substrate such as a polyimide film. By thereafter exposing the PANI film to deep UV radiation through a mask the initially conducting polyaniline is converted in the exposed areas to the non-conducting leucoemeraldine form. The starting point here is accordingly a conducting polymer material, the area resistance of which initially is 1 kiloohm/square, but which after the exposure obtains an area resistance of more than 1013 ohm/square. In this manner dielectric structures may be generated in an otherwise conducting matrix. FIG. 1 shows a MISFET according to Leeuw and al. comprising a polyimide substrate 1 with a PANI thin film which after exposure to UV light through suitable masks forms isolating structures 6 in the otherwise conducting thin-film material 3. The still conducting areas 3 in the PANI film define respectively the source and drain electrode of a MISFET transistor. Above the PANI film a further layer 4 is deposited in the form of a thin film of polythienylenevinylene or PTV which is an organic semiconductor material. This layer 4 substantially determines the electrical parameters of the MISFET transistor. A film 5 of polyvinyl phenol PVP which forms the gate isolator of the transistor and is opaque to UV radiation and visible light is deposited over the PTV film 4. Another PANI film is again deposited on the top of the PTV film 5 and patterned by radiation with UV light such that isolating structures 6 are formed. A still electrical conducting area 2 forms the gate electrode of the MISFET structure.
If several transistors of this kind as mentioned above shall be combined in integrated circuits realized in the form of stacked film layers, vertical current paths between for instance source and drain electrodes in a transistor and the gate electrode in another transistor must be used. Such vertical current paths may in principle be realized mechanically, for instance by depositing a metal film over vertically etched steps in the structure. Otherwise a close analogy is the use of throughplated holes in circuit boards for realizing a vertical connection between current paths on the upper and lower side of the circuit board.
The main object of the present invention is to provide improved fabrication methods for conducting connections and electrodes in microelectronic components and particularly microelectronic devices with large areas on flexible substrates by means of processes which combine high-volume fabrication at low costs. Particularly, it is an object of the invention to provide such fabrication methods that they may be used on layered physical devices, for instance in the form of a large number of adjacent stacked thin-film layers, thus generating three-dimensional circuit structures. The present invention will thereby make possible flexible and cheap, but simultaneously also singularly simple and precise fabrication of devices such as flat display devices, logic circuits, memory devices etc.
Further it is also an object of the invention to provide a method for erasing such three-dimensional circuit structures in situ, such that the material in the structures is converted back to an initial virgin state whereafter it by means of a suitable method may be reconfigured in the form of electrical conducting and semiconducting structures in three dimensions, but for instance with another pattern or another structure than the original.
The above-mentioned features and advantages are realized according to the present invention with a method which is characterized by applying to the separate layer an electric field with given field strength and/or characteristics adapted to the specific response of the material to the energy supplied by the field, modulating in each case the fields spatially according to a determined protocol which represents a predetermined pattern of electrical conducting or semiconducting structures in the relevant material structure, whereby in the layers in response to the energy supplied by the field two-dimensional electrical conducting or semiconducting structures are generated with the pattern predetermined by the protocol, and then optionally providing two or more layers in a stacked configuration, such that the composite matrix formed by separate adjacent layers is provided with electrical conducting or semiconducting structures in three dimensions.
Further it is according to the invention advantageous that the electric field is modulated spatially in a plane substantially parallel with a layer by means of an electrode device with patterned electrodes, the electrode device by selective supply of voltage to the electrodes according to the determined protocol generating electrical point or line potentials, which generate the electrical conducting or semiconducting structures.
It is according to invention advantageous that the stacked configuration is formed by two or more layers after generating the electrical conducting or semiconducting structure in each layer being combined into laminated multilayer structures which forms the composite matrix with electrical conducting or semiconducting structures in three dimensions.
It is according to the invention also advantageous positioning the multilayer formed by a lamination of two or more self-supporting layers into a stacked configuration. A layer is after the lamination to adjacent layers then preferably positioned such that two or more two-dimensional electrical conducting or semiconducting structures in the first-mentioned layer according to the protocol register with one or more two-dimensional electrical conducting or semiconducting structures in adjacent layers, whereby one or more vertical electrical conducting or semiconducting channels are generated in the cross-direction through the layers.
Finally, it is according to the invention advantageous providing an electrical conducting or semiconducting structure which forms a vertical channel through the layer according to the protocol, in electrical conducting or semiconducting connection with one or more two-dimensional electrical conducting or semiconducting structures in this layer, each channel preferably being generated with a conductivity or conduction mode which is constant between the layers or with a conductivity or conduction mode which varies between the layers.
A method for global erasing according to the invention is characterized by applying globally to the composite matrix an electric field with given field strength and/or characteristics adapted to the specific response of the material to the energy supplied by the field until the materials in the composite matrix in response to the energy supplied by the field in their entirety arrive in the electrical or non-conducting state.
An electric field generator/modulator is according to the invention characterized in that it comprises a first electrode means with a plurality of parallel strip electrodes provided in a plane, a second electrode means with a plurality of parallel strip electrodes provided at a distance from the first electrode means and superpositioned thereto in a second plane parallel with the first plane such that the electrodes mutually are substantially orthogonally oriented in a matrix-like arrangement, that the electrode means over cross-connection devices are connected with a controllable power supply, the electrical field generator/modulator in the space between the electrode means being adapted for receiving a thin-film material in the form of a discrete component or a continuous tape which without touching the electrode means continuously or intermittently is fed through the space with simultaneous positioning and alignment spaced apart from and between the electrode means in a plane substantially parallel thereto, whereby the electrical conducting or semiconducting structures can be generated according to a determined protocol and by means of point, line or area potentials is created between selected electrodes in the electrode means when the former over the cross-connection devices are supplied with electric power. Preferably are the electrodes in each electrode means provided on or in surfaces of respective substrates facing each other and/or in that connection preferably made as a part of the substrates and form conducting structures in the substrate material.
Further it is according to the invention advantageous that the distance between the electrode means is controllable depending on the thickness of the thin-film material.
Finally it is according to the invention advantageous that the electrodes in each electrode means are provided with a mutual distance between 0.1 xcexcm and 1.0 xcexcm and that the electrodes in each electrode means are formed with substantially constant width of 0.1 xcexcm to 1.0 xcexcm.
The invention shall now be explained in more detail in connection with a survey of its basic principles an with the use of exemplary embodiments in connection with the appended drawings, wherein
FIG. 1 shows a MISFET with the electrodes formed of photoconvertible material according to the prior art,
FIGS. 2a, b schematically respectively in section and plan view an embodiment of the electric field generator/modulator (EFGM) according to the invention and its use in a first step in the method for generating according to the invention,
FIGS. 2c, d schematically in respectively section and plan view EFGM as shown in FIGS. 2a, b and used in a second step in the method for generating according to the invention,
FIGS. 2e, f schematically in respectively section and plan view EFGM as shown in FIGS. 2a, b and used in a third step of the method for generating according to the invention,
FIG. 3 schematically the embodiment of the method for generating according to the invention, combined with a lamination of single layers into a multilayer structure,
FIG. 4 a section through a multilayer structure with conducting and semiconducting structures as generated by the steps shown in FIGS. 2a-f,
FIG. 5 a schematic section through a laminated multilayer structure which comprises conducting or semiconducting structures generated by the method according to the present invention,
FIG. 6 a schematic section through a diode structure generated by the method according to the present invention,
FIG. 7 a schematic section through a MOSFET structure generated by the method according to the present invention,
FIG. 8 a schematic section through a logic inverter structure based on the MOSFET structure in FIG. 7 and generated by the method according to the present invention,
FIG. 9 the equivalent diagram of an AND gate realized in CMOS technology,
FIGS. 10a-d in plan view sublayers in an AND gate structure generated by the method according to the invention and according to the equivalent diagram in FIG. 8 with the use of MOSFET structures as shown in FIG. 7,
FIG. 11 the AND gate structure in FIG. 10 as a stacked multilayer configuration, but exploded in the separate sublayers,
FIG. 12 schematically another variant of the AND gate structure in FIG. 10 and with the separate MOSFET structures provided mutually connected in a vertical configuration.